1. Field of the Invention
This invention relates to an arithmetic unit of an electronic computer.
2. Description of the Prior Art
Heretofore, there has been known such a divider unit as disclosed in Japanese Patent Laid Open Specification No. 96647/74. If a divisor is D and a dividend is N, this unit can obtain an approximation D.sub.t.sup.-1 of a reciprocal of the divisor D by referring to a table stored in a read-only memory and perform an operation of dt=1-D.times.D.sub.t.sup.-1. The unit further performs an operation of N.times.D.sub.t.sup.-1 with respect to the dividend N. N.times.D.sub.t.sup.-1 is grouped into an upper bit area Q (0) and a lower bit area R (0). This can be expressed by EQU N.times.D.sub.t.sup.-1 =Q(0), R(0) (1)
Every operation cycle satisfies the following relationship: EQU R(i)+Q(i)dt=Q(i+1), R(i+1) (2)
where i is a number of operation cycles and Q (i+1) and R (i+1) are upper area bits and lower area bits in (i+1) th operation cycle respectively. According to the equation (2), Q (0), Q (1), . . . , Q (i), . . . can be obtained and they form a quotient.
In an operation of the equation (2), since Q (i+1) of the right side is upper bits of a sum of the left side, an output obtained after passing through a multiplier, e.g. a carry save adder device arranged in a tree structure, may be in separate two forms, such as a carry and a sum, to calculate the left side. However, after R (i) is added to Q (i).times.dt according to the left side of the equation (2), the output must assume a single form by adding the carry and sum by an adding means. At this time, it is required to sequentially propagate carry signals in a direction from a lowermost bit order to an uppermost bit order. This prevents speedup of the operation. More specifically, according to the disclosure of Japanese Laid Open Specification No. 96647/74, when the equation (2) is repeated, a carry must be propagated to obtain Q (i+1) and R (i+1) through the adding means in every operation cycle.
To improve such a prior art, a carry look ahead adder may be employed as the adding means. In this case, the operation speed may be improved to some extent. However, since the carry look ahead adder has plural stages of gates therein, remarkable improvement in the operation speed cannot be expected.
The theory of Japanese Laid Open Specification No. 96674/74 will now be explained referring to FIG. 1. An arithmetic unit illustrated in the figure comprises a multiplier device 1 employing a carry save adder device of a tree structure, a carry save adder 2, an adder 3, a decoder 4 for decoding adjacent three bits inputted thereto, according to Table 1, and a selector 100A.
The operation of the unit is summarized as follows:
(1) dt=1-D.times.D.sub.t.sup.-1 is first obtained and fed to the multiplier device 1 (carry save adder device) as a multiplicand. PA1 (2) N.times.D.sub.t.sup.-1 is obtained and fed to the selector 100A. PA1 (3) The selector 100A divides N.times.D.sub.t.sup.-1 into an upper bit area Q (0) and a lower bit area R (0) and Q (0) and R (0) are fed to the decoder 4 and the carry save adder 2, respectively. PA1 (4) The decoder 4 receives an input of Q (0), decodes adjacent three bits according to Table 1 and transfers the decoded values to the carry save adder device 1 through a line 6. PA1 (5) The carry save adder device 1 performs multiplication of an output of the decoder 4 and dt according to the tree formation of the device 1 and outputs a sum and a carry to the carry save adder 2 through a line 8 and a line 9 respectively. PA1 (6) The carry save adder 2 receives the aforesaid three input data, i.e. sum through the line 8, carry through the line 9 and R (0), performs an operation of carry save addition and outputs, to the adder 3, a sum through a line 10 and a carry through a line 11. PA1 (7) The adder 3 performs an operation of addition of the sum and the carry through the lines 10 and 11 respectively and outputs the result to the selector 100A through a line 12. PA1 (8) The selector 100A receives the output of the result of the addition, divides the output into upper data Q (1) and lower data R (1) and outputs Q (1) to the decoder 4 and R (1) to the carry save adder 2. PA1 (9) Q (2) and R (2) are obtained by carrying out the steps 4 to 8. Similarly, Q (3), R (3), Q (4), R (4) . . . are obtained. PA1 (10) The upper data Q (i) (where i=0, 1, 2, . . .) obtained in each cycle is outputted to the outside so as to utilize it as a partial quotient. PA1 a decoder for directly providing decoding conditions each for respective corresponding bits of the data X and Y without carrying out adding operation (X+Y) of the data X and Y, carrying out the decoding according to said decoding conditions and outputting selecting signals for given rates relative to the data Z; and PA1 a device for obtaining values corresponding to products of the data Z and said given rates selected by said respective signals and carrying out adding operation of said values.
As apparent from the foregoing description, the adder 3 is essential in the divider unit of the prior art. However, it is apparent that the employment of the adder 3 lengthens the operation time of the arithmetic unit as much as the operation time of the adder 3.
This problem involved in the prior art divider unit is also encountered in a known multiplier unit. A block diagram of the known multiplier unit is illustrated in FIG. 2. In the figure, the same numerals and letters designate the same contents as in FIG. 1. Inputs X and Y are subjected to operation of addition (X+Y) by an adder 5. A decoder 4 carries out decoding according to Table 1 and the result is inputted to a multiplier device 1 formed of a tree-structured carry save adder device. The multiplier device 1 performs an operation based on data Z inputted from the outside and the result obtained from the decoder 4 and it outputs to the outside the result of (X+Y).times.Z. This unit requires an operation of addition of X and Y through all bits thereof to perform addition of (X+Y). The time required to perform addition of (X+Y) accounts to considerable length so that substantial improvement cannot be expected as far as the addition operation of (X+Y) has been essential.